Next: Verifying HDL Code
Automating FPGA Design
The HDL Workflow Advisor in HDL Coder automates the workflow for implementing your MATLAB algorithms and Simulink models into Xilinx and Altera FPGAs. The HDL Workflow Advisor integrates all steps of the FPGA design process, including:
- Checking the Simulink model for HDL code generation compatibility
- Generating HDL code, an HDL test bench, and a cosimulation model
- Performing synthesis and timing analysis through integration with Xilinx ISE and Altera Quartus II
- Estimating resources used in the design
- Back annotating the Simulink model with critical path timing
Back annotating a Simulink model with critical path timing. The HDL Workflow Advisor highlights critical path timing in Simulink to help identify speed bottlenecks and improve design performance.
You can view a postsynthesis timing report and back annotate the Simulink model to identify timing-constraint bottlenecks. This integration with synthesis tools enables rapid design iterations and significantly reduces FPGA design cycle time.